1. Field of the Invention
The present invention relates to a package for mounting a semiconductor chip, that is, a semiconductor package, a method of production of the same, and a semiconductor device comprised of that semiconductor package and a semiconductor chip mounted in it.
2. Description of the Related Art
Semiconductor devices are being made increasingly denser in many applications. In accordance with this, when providing interconnect patterns in close proximity, it is important to prevent crosstalk noise between interconnects and fluctuations in potential of power lines etc. In particular, in the case of a semiconductor package mounting a high frequency semiconductor chip required for high speed switching operations, crosstalk noise occurs more easily along with a rise in the frequency. Further, high speed on/off operations of switching elements also cause switching noise. Due to this, the potential of the power lines etc. fluctuates more easily.
In the past, as means for eliminating such problems, a separate chip capacitor or other capacitor was mounted in a semiconductor package as a bypass capacitor for eliminating unnecessary coupling between circuits by signal lines or power lines (decoupling).
The method of the related art, however, suffered from the following problems.
First, the degree of freedom of design of the interconnect patterns falls along with mounting of a separate chip capacitor etc.
Further, if the interconnect distance connecting a chip capacitor and semiconductor chip is long, the inductance becomes larger and the decoupling effect of the chip capacitor can no longer be obtained. Therefore, the chip capacitor etc. has to be mounted in as close proximity to the semiconductor chip as possible. The size of the chip capacitor etc., however, restricts the mounting position, so there were also limits to the proximity of arrangement with respect to the semiconductor chip.
Further, if mounting a chip capacitor or other capacitor in a semiconductor package, the package unavoidably becomes larger in size and heavier in weight. This runs counter to the current trend of the reduction of size and weight. In this regard as well, there were limits to measures through reduction of size of the chip capacitor etc.